Driving Multiple FPGAs and Fanout (Cyclone III)

You'll have to face the same signal integrity problems as with any other unterminated data bus system. Particularly the stubs loaded with the FPGA I/O capacitance will cause serious signal reflections. Series resistances, either at the chips or near the board connector can help to reduce it. You should use a moderate bus speed anyway.

There's no principal difference between LVTTL and LVCMOS I/O standard on the FPGA side, it's just a different way to calculate the I/O drive strength according to the different thresholds involved with the standard.

P.S.: From existing single ended bus standards, Cyclone III supports 3.3V PCI and PCI-X. This is a way to provide a specified standard without external bus drivers.