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Altera_Forum's avatar
Altera_Forum
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16 years ago

DQS Pin Assignment Problem in EP4SGX530 FPGA

Hi,

I am doing the Pin Planning and analysis for my DDR3C pin assignment in Altera EP4SGX530HH35C2ES FPGA ( 1152 Package). I am seeing following error message while doing the I/O Check in the Pin Planner tool.

Error: Bidirectional pin rxd_ddr3_dqs[0] with a pseudo-differential I/O standard must use the output enable control signal on the output buffer

Followings are my qsf file content for this : # ######################### Just for convenience, I am showing only one dqs pin assignemnt.

set_location_assignment PIN_AM10 -to rxd_ddr3_dqs_n[0]

set_location_assignment PIN_AL10 -to rxd_ddr3_dqs[0]

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to rxd_ddr3_dqs[0]

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to rxd_ddr3_dqs_n[0]

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to rxd_ddr3_dqs[0]

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to rxd_ddr3_dqs_n[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to rxd_ddr3_dqs[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to rxd_ddr3_dqs_n[0]

# #####################################

I have used DQS for x4 for 1152. Same pin mapping corresponding to F1517 package is passing in the I/O check.

I am not able to fix this issue . I tried all the related option value for this pin in the I/O assignment Editor, but still I/O check is failing. Can you Please suggest any solution for this.

Thanks

Rakesh

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Note sure if this helps but I seem to have a whole series of:

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[64]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[65]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[66]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[67]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[68]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[69]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[70]

    set_instance_assignment -name DQ_GROUP 9 -from ddr3_rdimm_a_dqs[8] -to ddr3_rdimm_a_dq[71]

    set_instance_assignment -name DQSB_DQS_PAIR ON -from ddr3_rdimm_a_dqsn[8] -to ddr3_rdimm_a_dqs[8]

    that I am going to go look for more info on.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi

    I have the same problem in my Arria II Gx Development Kit when I try to build a Qsys system to access a DDR3. 

    
Error (176183): Bidirectional pin ddr3_dqs with a pseudo-differential I/O standard must use the output enable control signal on the output buffer

    I have run the tcl file for pin assignment and see the following text in my qsf file. 

    
set_instance_assignment -name OUTPUT_ENABLE_GROUP 849089556 -to ddr3_dq
...
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq
...
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq
...
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs -to ddr3_dq
...

    Does anyone know how to solve this problem?

    Thanks.