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Altera_Forum
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16 years ago

DQS Pin Assignment Problem in EP4SGX530 FPGA

Hi, I am doing the Pin Planning and analysis for my DDR3C pin assignment in Altera EP4SGX530HH35C2ES FPGA ( 1152 Package). I am seeing following error message while doing the I/O Check in the Pin ...
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Altera_Forum
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13 years ago

Hi

I have the same problem in my Arria II Gx Development Kit when I try to build a Qsys system to access a DDR3. 


Error (176183): Bidirectional pin ddr3_dqs with a pseudo-differential I/O standard must use the output enable control signal on the output buffer

I have run the tcl file for pin assignment and see the following text in my qsf file. 


set_instance_assignment -name OUTPUT_ENABLE_GROUP 849089556 -to ddr3_dq
...
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq
...
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq
...
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs -to ddr3_dq
...

Does anyone know how to solve this problem?

Thanks.