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Honored Contributor

16 years ago

DQS Pin Assignment Problem in EP4SGX530 FPGA

Hi, I am doing the Pin Planning and analysis for my DDR3C pin assignment in Altera EP4SGX530HH35C2ES FPGA ( 1152 Package). I am seeing following error message while doing the I/O Check in the Pin ...

Altera_Forum

Honored Contributor

13 years ago

I solved this fitter problem yesterday.

The solution for this problem can be referred to the design example in alterawiki.

http://www.alterawiki.com/wiki/design_example_-_arria_ii_gx_ddr3_sdram_altmemphy_300mhz_x16

Just follow the instructions and this error should not appear.

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DQS Pin Assignment Problem in EP4SGX530 FPGA

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