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I'm working on a Stratix III design using DPA on links between FPGAs on the same board. My question is: is it really necessary to have to dynamically train each channel to achieve word alignment? i.e. can't it just be set statically and assumed to always be in the same alignment?
Having monitored the transmitted signals, the clock and data always have the same phase relationship (msb aligned with rising edge of clock) so I don't quite see why I would assume it could be anything different.
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It would be easy if there is no external factor that can affect the characteristic of the signals. In real world, this cannot be assumed. Temperature and voltage variations can cause changes to signal's charateristics. Having to train the channels dynamically is the way to go.
Hope this helps.
Honored Contributor
