DPA Word Alignment

No, it's not that fast but if I stick with a SERDES/DPA approach I always have the option of pushing things faster later on.

What I have discovered is that bit 6 (msb) on the Tx side comes out in bit 3 on the Rx side which happens to be the middle bit of the 7. Can this be explained?

As far as I can tell from the Stratix III documentation this is what should happen

Tx clock/data:

/^^^^^^^^^\____________/^^^^^^^^\_____________/

<6><5><4><3><2><1><0><6><5><4><3><2><1><0>

Rx data:

<...............6543210............><...............6543210............>

I'm getting:

Tx clock/data:

/^^^^^^^^^\____________/^^^^^^^^\_____________/

<6><5><4><3><2><1><0><6><5><4><3><2><1><0>

Rx data:

<................2106543............><................2106543............>