Does User clock frequency in QSYS for HPS-to-FPGA clock work?

We have a project using Quartus 13.1 and are trying to configure the HPS-to-FPGA user0 clock to be 50 MHz (instead of 100). The dialog seems to take 50 MHz fine, but when we generate the handoff files for the FPGA, there doesn't seem to be a difference between the generated files. Specifically, we get the following in the pll_config.h file:

#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)# define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)# define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)# define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)# define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)# define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)# define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)# define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(15)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		(1)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		(0)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		(1)# define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		(0)