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Altera_Forum
Honored Contributor
Honored ContributorDoes User clock frequency in QSYS for HPS-to-FPGA clock work?
We have a project using Quartus 13.1 and are trying to configure the HPS-to-FPGA user0 clock to be 50 MHz (instead of 100). The dialog seems to take 50 MHz fine, but when we generate the handoff fil...
Altera_ForumHonored Contributor
Honored ContributorHi,
I don't know why Qsys didn't generate it as configured, but you can edit the pll_config.h manually and set the proper settings for your application. But be patiant, all the frequencies you configure have to fit to the operating range of the device (have a look in the datasheet). More about clock customization can be found here: http://www.rocketboards.org/foswiki/documentation/preloaderclockingcustomization
