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Altera_Forum
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12 years ago

Does User clock frequency in QSYS for HPS-to-FPGA clock work?

We have a project using Quartus 13.1 and are trying to configure the HPS-to-FPGA user0 clock to be 50 MHz (instead of 100). The dialog seems to take 50 MHz fine, but when we generate the handoff fil...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

I was trying to find out the value of f2h_axi_clocl, h2f_lw_axi_clock but couldn't locate the value in qsys. Can anyone please let me know or correct me if anything wrong i am doing.

Thanks,

Pankaj