Does internal CRC error detection effect design?

I agree with FvM that the Quartus statement doesn't make much sense. amilcar's interpretation might make a little bit more sense, but IMHO, not really too much.

The CRC error logic uses its own clock, has a configurable clock divisor, and it is connected to user logic only optionally. So, in the worst case, it would affect performance of that user logic connected to the CRC block. If at all.

SIII handbook has this sentence:

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Using CRC error detection for the Stratix III family has no impact on fitting or performace of your device.

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