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Altera_Forum
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15 years ago

Does a configured FPGA need loading a configure file and initialization at power on?

Hi, Everyone,

I am a CPLD user and thinking to use a FPGA (Cyclone II) for my next design. I have a FPGA beginer's question. Does a programmed/configured FPGA (Cyclone II or III) need to load a configure file and go through a initialization process at every power on of the circuit? If that is true, the I/O output pin will be pull-up to VccIO through a weak pull-up resistor during the loading configure file and initialization process (as mentioned on the Cyclone II user's manual). What should I do to prevent the output I/O driving high? A CPLD does not have this problem. May be I am confused by the word "configure". Please, if anyone, give me an answer. Thank you.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    There are multiple methods for loading the configuration data. If you have a micro already, in your design, then having a micro due the job is usually preferable, because you already have flash for it's program space. However if you don't the various families also support self programming through a serial flash device. (Active Serial Mode)

    Although Altera sells their own flavor of the serial flash devices, most standard serial flashes work for this purpose.

    (See numonix/ST)

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you Cris72. Now I have a better understanding the difference between CPLD and FPGA.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Altera FPGAs are based on SRAM technology. So, there's no way to store non-volatile data inside them.

    The jtag is used for debugging or as ISP for the external eprom: in this latter case the fpga simply act as a bridge between jtag interface and the eprom connected to its pins.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you Cris72. I though I can use a FPGA (Cyclone II, or III) as a big CPLD. Based on what you say, I have to have a EPROM or a host microprocessor to hold the configuration file and down load this file to the FPGA at every power up. The FPGA will lost the configure information when it is power down. Is there no place to hold this information inside the FPGA? If that is true, what is the purpose to use a JTAG to program the FPGA? I though it is the same as I program a CLPD using a JTAG cable.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Does a programmed/configured FPGA (Cyclone II or III) need to load a configure file and go through a initialization process at every power on of the circuit?

    --- Quote End ---

    That's true. FPGA configuration is volatile and it needs to be loaded at every power up or reset, for example from an external eprom or host microprocessor.

    Clearly this requires at least a minimal amount of time when the fpga is a non-configured state and user I/O pins have a weak pull up.

    If you really need a pin not to go high you can use a pull down stronger than the internal one or add an external inverting stage. The best solution is to design the rest of the circuit in order to comply with fpga characteristics.