Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThank you Cris72. I though I can use a FPGA (Cyclone II, or III) as a big CPLD. Based on what you say, I have to have a EPROM or a host microprocessor to hold the configuration file and down load this file to the FPGA at every power up. The FPGA will lost the configure information when it is power down. Is there no place to hold this information inside the FPGA? If that is true, what is the purpose to use a JTAG to program the FPGA? I though it is the same as I program a CLPD using a JTAG cable.
Thanks.