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Does a programmed/configured FPGA (Cyclone II or III) need to load a configure file and go through a initialization process at every power on of the circuit?
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That's true. FPGA configuration is volatile and it needs to be loaded at every power up or reset, for example from an external eprom or host microprocessor.
Clearly this requires at least a minimal amount of time when the fpga is a non-configured state and user I/O pins have a weak pull up.
If you really need a pin not to go high you can use a pull down stronger than the internal one or add an external inverting stage. The best solution is to design the rest of the circuit in order to comply with fpga characteristics.
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