Do you use LPMs for your LFSRs?

Thanks again Kaz. I can't quite see where I was going wrong

process(reset,clock)
begin
if reset = '1' then
   shift_reg <= "0001"; -- seed
elsif rising_edge(clock) then
   shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps
   shift_reg(2) <= shift_reg(1); -- shift
   shift_reg(3) <= shift_reg(2);
end if;
output    <=    shift_reg;
end process;

When I simulate this the output is always 1?

Either way you end up with shift register.

Inference is easier and portable.

example

--

signal shift_reg : std_logic_vector(33 downto 1);

process(reset,clk)
begin
if reset = '1' then
   shift_reg <= '0' & x"28EA5CB1"; -- seed
elsif rising_edge(clk) then
   shift_reg(1) <= shift_reg(20) xor shift_reg(33); -- taps
   shift_reg(33 downto 2) <= shift_reg(32 downto 1); -- shift
end if;
end process;

the final output could be any number of bits you choose from the shift_reg

however, my favorite method is read a text file.