DMA doesn't write due to high write waitrequest

I have an SOPC builder system that implements the design sample in ug_pci_express.pdf but with a different BAR setup and address bases. I've modified the testbench to reflect this, however I'm running into a weird issue:

In dma_ctrl, the commands are received for the dma transfer and the read starts (successfully, getting the data). However, the write_waitrequest is always asserted, thus the write never starts.

Any ideas?

I attached a screenshot of the sopc builder with the connections and address offsets, and the modified bfm driver for the testbench.

Thanks,

Richard