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Altera_Forum's avatar
Altera_Forum
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15 years ago

division 2 integer value and output to the output reg

Hi, Is it can not direct using the division '/' in verilog?.. I notice that the result of division between two integers number and stored in the out reg gives red color words shown in Signal Ta...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The question, if your code compiles correctly is answered by the synthesis tool, not Signaltap. If the code compiles correctly, you can expect that it has been accepted. You should also find an information about inferred dividers in the compilation messages and the report.

If a signal is not recognized by Signaltap, you haven't selected the right object. You should be able to select the output of the divider entities in the Signaltap hierarchy browser. As a general hint, try to access a signal at it's source, not as a wire in a different design entity.