Forum Discussion
ContributorDiscrete RSU User Logic
Regular ContributorHi,
I would recommend you to generate the Dual Configuration IP in VHDL which will be more easier to use rather than the ATOM module.
- JohnT_Altera
Attach is the IP generated. You can observed that inside the "RU" folder, where RU_inst.vhd is calling RU_inst.v file.
jozephka99Thank you for your reply @JohnT_Intel. I don't know either the signal informations. I just wanted to perform discrete RSU. Also I'm already started to use dual config IP. So far, I'm able to set config_sel and reconfig the device in either CFM0 or CFM1/2. I think this is enough for RSU. But if you know how to do error checking and fallback situations it is also useful for me. But the main issue that I working on now how I can write the .rpd file into CFM sectors. I can use the on-chip flash IP but I don't know the form of data that I write into CFM. Can I write the data as well as in the .rpd file? In AN741 the data's MSB and LSB was swapped, do I have to swap too? I'll use UART interface, the data came as bytes. I'm planning the write the data into RAM first. When the data came, then I'll write it to CFMs. Also for testing I want to initialize the RAM for not doing the data sending stuff for now. So anything you know about my situation will be helpful.
Thanks.
- jozephka99
For the ones who wonder the use of dual boot configuration IP, here is the example VHDL code:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity manual_rsu is port( clk : in std_logic; reset : in std_logic; leds : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of manual_rsu is component rsu_pd is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n dual_boot_avalon_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address dual_boot_avalon_read : in std_logic := 'X'; -- read dual_boot_avalon_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dual_boot_avalon_write : in std_logic := 'X'; -- write dual_boot_avalon_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component rsu_pd; signal db_avalon_address : std_logic_vector(2 downto 0) := (others => 'X'); signal db_avalon_read : std_logic := 'X'; signal db_avalon_writedata : std_logic_vector(31 downto 0) := (others => 'X'); signal db_avalon_write : std_logic := 'X'; signal db_avalon_readdata : std_logic_vector(31 downto 0) := (others => '1'); signal cnt : integer := 0; begin rsu : component rsu_pd port map ( clk_clk => clk, -- clk.clk reset_reset_n => reset, -- reset.reset_n dual_boot_avalon_address => db_avalon_address, -- dual_boot_avalon.address dual_boot_avalon_read => db_avalon_read, -- .read dual_boot_avalon_writedata => db_avalon_writedata, -- .writedata dual_boot_avalon_write => db_avalon_write, -- .write dual_boot_avalon_readdata => db_avalon_readdata -- .readdata ); process (all) begin if(reset = '0') then leds<= "11001100"; cnt <= 0; elsif(rising_edge(clk)) then cnt <= cnt + 1; if(cnt = 0) then leds <= "00011000"; db_avalon_address <= "001"; db_avalon_writedata <= x"00000001"; -- set config_sel_overwrite and config_sel for boot from CFM0 db_avalon_read <= '0'; db_avalon_write <= '1'; elsif(cnt = 3) then -- write operation needs 3 cycle db_avalon_read <= '0'; db_avalon_write <= '0'; elsif(cnt = 4) then db_avalon_address <= "011"; -- read busy signal db_avalon_read <= '1'; db_avalon_write <= '0'; elsif(cnt = 5) then -- read operation needs 1 cycle db_avalon_read <= '0'; db_avalon_write <= '0'; elsif(cnt = 6) then -- read data came in 3th cycle db_avalon_write <= '0'; db_avalon_read <= '0'; leds(0) <= db_avalon_readdata(0); leds(7 downto 1) <= (std_logic_vector(to_unsigned(cnt, 7))); elsif(cnt = 7) then db_avalon_address <= "000"; -- trigger reconfig db_avalon_writedata <= x"00000001"; -- hold nconfig min 250ns, 4 cycle at 12 MHz db_avalon_read <= '0'; db_avalon_write <= '1'; elsif(cnt > 7) then end if; end if; end process; end rtl;And in platform designer:
You can reach the dual boot IP's addresses and relevant bits from page 62 on:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf
