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I look at an example part number AD9912 which can generate up to 400 MHz.
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Ok - "1 GSPS Direct Digital Synthesizer with 14-Bit DAC".
Now what you should do is go and implement something similar using the Altera NCO compiler. That'll give you a good understanding on the correspondence between the FPGA solution and the DDS solution.
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Now that when FPGAs are replacing almost every hardcore microcontrollers, designing these applications around FPGAs will open a lot of avenues.
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While this statement is true, you need to be very careful when it comes to
analog interfacing; the source of the clock to the analog-to-digital converter (ADC), or digital-to-analog converter (DAC) is critical. For DACs, you also need to carefully consider the filtering that follows the DAC output (for example, see the DDS filter design for the AD9956 in the links above).
Low-jitter in the clock reference to an ADC or DAC is critical to their operation. The links I sent above are for a 1GHz ADC design, and I would never consider using the ADC clock from an FPGA PLL. The same consideration should be made when working with a DDS or DAC. The clocking of this component should be carefully designed. It might appear to be convenient to drive a DAC clock from an FPGA PLL output, but you would first need to measure whether it meets your requirements.
Similarly, when it comes to processor applications, FPGA soft-core processors are not always the correct solution. In the design for the links I sent, I used a $100 PowerPC processor (500MHz clock rate) to interface to much more expensive FPGAs. I would not consider using a soft-core processor in that particular application, as I did not want to use logic resources on a soft-core processor, and the performance of a soft-core solution was inadequate. However, if I was building a simple digital I/O board and needed simple control, I'd have no problem using a NIOS processor in a Cyclone device.
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In this regard, as a designer and an academician, I am trying to design this with maximum frequency within the limits of Niquist Criterion and see how the frequency can be increased. I shall start the design and update you on each and every stage.
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If you want the current state-of-the art limit in DACs and ADCs, go and check out the devices from Micram - their Vega ADCs and DACs operate at 30GHz clock rate.
http://www.micram.com/index.php/products/vega I'll be testing their ADC evaluation board next week.
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First of all, I am going by the PPT and then go for other references. If quick links are available, pl send them across.
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Read this paper and the slides (download the .zip, as it has the original powerpoint and its nicer to read)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip)
Read through the warnings with regard to the use of NCOs and their harmonic content. If you want the MATLAB scripts for any of the figures, just ask, and I'll post a link.
Cheers,
Dave
Honored Contributor
