Direct Digital Synthesis

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I bought the DE0 board from Terasic ....

... I shall try the fastest DAC of Analog Devices ...

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Check the logic levels of the DAC. The higher-speed ones use LVDS. You would need to check whether the DE0 pins can be configured for LVDS.

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I shall get back to you during the progress of the design. I also referred Jan 2004 of Elektor ( Indian Reprint ) as I am a regular reader since 1983. I shall try to scan and send the pages of it.

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Sure. Just send it to the email address that is my Forum name.

Cheers,

Dave

Hi Dave,

I bought the DE0 board from Terasic and would like to develop the DDS initially.

Based on the other interfacing components that can be connected to the Board, I would like to develop the circuit right from the frequency word at the input and the DAC at the outputs.

As suggested, I shall try the fastest DAC of Analog Devices. I shall get back to you during the progress of the design. I also referred Jan 2004 of Elektor ( Indian Reprint ) as I am a regular reader since 1983. I shall try to scan and send the pages of it.

With Kind Regards,

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Pl reply if the PowerPC option is better than ARM.

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The PowerPC processor was selected to meet the following requirements; PCI bus, DDR bus, local bus, and floating-point unit. The DMA performance of an evaluation board was then tested. The PowerPC on the CARMA board meets all the performance requirements, and has a pretty low processor workload.

Very few ARM processors meet the above requirements (most lacked an FPU, and the independent buses).

The Freescale PowerPC documentation is good, their engineers directly contribute to the U-Boot bootloader group and to the Linux kernel. The same cannot be said for many of the ARM processor companies.

Your requirements will be different, and its likely you can find an ARM processor to meet your requirements. I personally find the PowerPC support better than ARM.

Cheers,

Dave

Dear Mr.DWH,

I saw the CARMA board design circuit which was developed by gdatech.

Did you check its performance and how was the speed using PowerPC.

It is true that my intention is of research interest around DDS and at the first place I am looking at a good performance DAC type and then moving back to the rest of the blocks of DDFS and of course around Altera Products only.

Pl reply if the PowerPC option is better than ARM.

With Kind Regards,

S.Saravanan

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I have gone thru all the links of ~dwh which were very useful.

I shall see all the files that were downloaded from the links and will start the work.

I shall let you know if the matlab code will be useful for me at this stage of my work.

Nice that all the designs are around Altera Products. The NCO was very useful.

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Let me know if you need specific examples and I can code something up, or explain what you need to do.

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I am unable to see your website in caltech.

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What was not working?

Cheers,

Dave

Dear Dave,

I have gone thru all the links of ~dwh which were very useful.

I shall see all the files that were downloaded from the links and will start the work.

I shall let you know if the matlab code will be useful for me at this stage of my work.

Nice that all the designs are around Altera Products. The NCO was very useful.

I am unable to see your website in caltech.

With Kind Regards,

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I look at an example part number AD9912 which can generate up to 400 MHz.

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Ok - "1 GSPS Direct Digital Synthesizer with 14-Bit DAC".

Now what you should do is go and implement something similar using the Altera NCO compiler. That'll give you a good understanding on the correspondence between the FPGA solution and the DDS solution.

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Now that when FPGAs are replacing almost every hardcore microcontrollers, designing these applications around FPGAs will open a lot of avenues.

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While this statement is true, you need to be very careful when it comes to analog interfacing; the source of the clock to the analog-to-digital converter (ADC), or digital-to-analog converter (DAC) is critical. For DACs, you also need to carefully consider the filtering that follows the DAC output (for example, see the DDS filter design for the AD9956 in the links above).

Low-jitter in the clock reference to an ADC or DAC is critical to their operation. The links I sent above are for a 1GHz ADC design, and I would never consider using the ADC clock from an FPGA PLL. The same consideration should be made when working with a DDS or DAC. The clocking of this component should be carefully designed. It might appear to be convenient to drive a DAC clock from an FPGA PLL output, but you would first need to measure whether it meets your requirements.

Similarly, when it comes to processor applications, FPGA soft-core processors are not always the correct solution. In the design for the links I sent, I used a $100 PowerPC processor (500MHz clock rate) to interface to much more expensive FPGAs. I would not consider using a soft-core processor in that particular application, as I did not want to use logic resources on a soft-core processor, and the performance of a soft-core solution was inadequate. However, if I was building a simple digital I/O board and needed simple control, I'd have no problem using a NIOS processor in a Cyclone device.

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In this regard, as a designer and an academician, I am trying to design this with maximum frequency within the limits of Niquist Criterion and see how the frequency can be increased. I shall start the design and update you on each and every stage.

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If you want the current state-of-the art limit in DACs and ADCs, go and check out the devices from Micram - their Vega ADCs and DACs operate at 30GHz clock rate.

http://www.micram.com/index.php/products/vega

I'll be testing their ADC evaluation board next week.

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First of all, I am going by the PPT and then go for other references. If quick links are available, pl send them across.

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Read this paper and the slides (download the .zip, as it has the original powerpoint and its nicer to read)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip)

Read through the warnings with regard to the use of NCOs and their harmonic content. If you want the MATLAB scripts for any of the figures, just ask, and I'll post a link.

Cheers,

Dave

In that case, have a look at this tutorial from Analogue devices, it is very comprehensive.

http://www.analog.com/static/imported-files/tutorials/450968421dds_tutorial_rev12-2-99.pdf (http://www.analog.com/static/imported-files/tutorials/450968421dds_t)

you better copy/paste this link.

Bear in mind the method of virtual LUT and its phase resolution. the way a limited LUT can be interpolated resulting in a virtual very large LUT.

Notice the concepts of phase resolution, amplitude resolution, etc and the way LSBs of accumulator are discarded.

Note also the phase continuity of dds when changing tuning. However many people are not aware that this continuity only holds one side of frequency polarity i.e. changing from + to - or the reverse breaks the phase.

Thanks for your reply.

I look at an example part number AD9912 which can generate up to 400 MHz. Now that when FPGAs are replacing almost every hardcore microcontrollers, designing these applications around FPGAs will open a lot of avenues.

In this regard, as a designer and an academician, I am trying to design this with maximum frequency within the limits of Niquist Criterion and see how the frequency can be increased. I shall start the design and update you on each and every stage.

First of all, I am going by the PPT and then go for other references. If quick links are available, pl send them across.

WIth Kind Regards,

dwh,

I agree you are aiming at practical scenarios.

I believe the original post is more of teaching or research intention. As such I will think of the full versatility of a DDS including tuning, resolution of microhz, phase control ...etc. Thus the original post must be more clear about the purpose.