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Honored Contributor
Honored ContributorDifficulty in Connecting entities in Quartus II
Hi guys.... Iam a newbie. I entered into FPGA field just 40 days back. Iam using Altera's Quartus II tool for compilation and downloading the code. I have declared two entities differently in...
Altera_ForumHonored Contributor
Honored ContributorYOu could make a block diag (schematic) and create symbols for each of these, then insert them in to the schematic and provide the interconnections.
or You can write athird file, then 'reference' both of the other two modules (VHDL and Verilog do this differently) and then in this new module, interconnect the two as you desire. Get a good reference book on multiple file coding, or look at a few examples by others.
