Difficulty in Connecting entities in Quartus II

YOu could make a block diag (schematic) and create symbols for each of these, then insert them in to the schematic and provide the interconnections.

or

You can write athird file, then 'reference' both of the other two modules (VHDL and Verilog do this differently) and then in this new module, interconnect the two as you desire.

Get a good reference book on multiple file coding, or look at a few examples by others.