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Altera_Forum
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10 years ago

Differential input pair LVDS for the ADC5272 in Cyclon 3

good evening ! background: i am now trying to design a new develop FPGA( CYCLONE 3 EP3C40Q240C8) board. it has 2 ADC chips(ADS 5272 http://www.ti.com/lit/ds/symlink/ads5272.pdf ) which o...
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Altera_Forum
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10 years ago

There is plenty of LVDS I/O to allow you to interface that ADC to your chosen Cyclone III.

I recommend you connect the ADCLK and LCLK LVDS pairs to dedicated clock input pins. These dedicated clock input pins can be configured for LVDS operation and, as someone has already pointed out, feed directly onto clock networks internally. They can also feed PLLs if required. They offer good flexibility in that respect.

The other 8 OUTx p/n pairs can just feed 'ordinary' I/O. Refer to the pin information for the cyclone® iii ep3c40 device (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone3/ep3c40.pdf) spreadsheet for that part. The 'Optional Funtion(s)' column identifies all he I/O that can be used as an LVDS pair. All the 'DIFFIO_xx' are suitable - plenty to chose from. Similarly, 'DIFFCLK_xx' are suitable dedicated clock input pairs.

Make sure you connect all these signals, including the clocks, to banks powered at 2.5V.

Regards,

Alex