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Altera_Forum
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14 years ago

different width dual port ram from VHDL template

Dear all, In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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As long as the implemented bitwidths are within the supported range of the respective RAM type, there should be not a single RAM cell wasted. At least I didn't observe this in my RAM designs.

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It depends what is meant by "support". I had a design of ram in stratix IV as follows:

portA: 16bits x 256

portB: 512bits x 8

resource required: 140 M9Ks !!! if read/write on both ports but reduced to 20 M9Ks if write only/read only.

The issue of intrinsic block support is not always visible to the user. Ofcourse if the block is made to support the width there would be no waste. It is when it does not and the tool does not tell.