different width dual port ram from VHDL template

but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. If you see in the code attached, i have implemented sort of serialization, but it generates quite a lot of logic around the memory cell itself.

N.b. i still did not find any method how to tell to compiler via tcl commands to instantiate that entity as m4k cell. Whereas when using megawizard on one of the screens it asks you into which memory you want to implement it. Afaik this is quite important as I've read in one of altera documents that m4k memory registers writes on falling edges of write signal. I just hope that I did not understand correctly and this behaviour is only for asynchronous memories, which is not my case