different width dual port ram from VHDL template

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In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in instauration of dual port memory with both ports having 32bits and lots of glue logic around.

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I'd recommend keeping both ports with the same widths, and then just implementing your own serializer logic on the 1-bit side, i.e., read a 32-bit value and serialize it as 1-bit data.

Cheers,

Dave