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The TS7400 does not use a PC104 interface. It has this 20 bit DIO bus coming off their CPLD going to a 40 pin header (there are other useful signals in there like a SPI interface and a uart interface, but that is not interesting to our discussion). You can't connect to the cpu directly (which would have been way more efficient).
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Ok. Your bit-banged bus proposal makes sense given the hardware limitations.
The lesson to take from this experience is to define the interfacing requirements before buying any hardware :)
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As an aside, my next project is to design our own cpu board and then we can get much more efficiency.
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Since that particular design is not on-topic for the Altera Forum, email me off-list with your requirements and thoughts, and I'll give you feedback.
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My original efforts in designing for programmable logic started only about 2 months ago. I learn Quartus, Verilog, SystemVerilog, and how to write testbenches. At the time I thought timing would not be a factor because of the slow speeds. I can see now that timing is everything, it does not solve itself automatically, even in a simple slow design.
I had written testbenches for each of my modules all the way up to the final top level testbench. It does exactly what you suggest, emulates the bus, writing addresses, writing data, reading data and using approximately the same timing as I discovered on the scope. So the functional models have been working from the very early days, according to ModelSim. Not having a problem with that. When running on the FPGA then I discovered the problems with timing and registers not doing what ModelSim said they should.
I did in fact write a state machine for the main IO at the top level and it does what you suggested. It basically captures the address in a register during the ale pulse (I have been trying different suggestions on that to use it to gate the main clock so that all timing is based on the one 14 MHz clock). Those function correctly in the test bench.
I'm coming up to speed on TimeQuest and SDC files and the Timing Advisor. Following its suggestions I have been able to get the slack time to be positive in all but one signal and that one is off by only a couple picoseconds. but I have not tried that in the hardware yet.
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Excellent effort!
If you can post a zip file with your code and testbenches, then please do. If you're not sure you want to post that material to the Altera forum, then email them to me, and direct me to the parts of the code you are unsure about, and I'll take a look (my forum name is my email address).
Cheers,
Dave
Honored Contributor
