Different results on hardware compared to simulator

You really want to keep everything driven off _one_ clock in the system. This means oversampling ale etc, detecting edges and doing the appropriate thing.

Normally I'd use one of the PLLs to generate a clock 4 or 5 (or more) * the rate of what I'm sampling, but if your data is stable for 1us and ALE is 1us wide then the 14MHz clock should be sufficient.

A simple example follows of how I'd do your address latching and incrementing in VHDL....

 
signal addr_in_d, addr_in_2d : std_logic_vector(7 downto 0);
signal ale_d, ale_2d, ale_3d : std_logic;
signal address : std_logic_vector(10 downto 0);
 
  :
 
process(clk,rst)
begin
if(rst = '1') then
  addr_in_d <= (others => '0');
  addr_in_2d <= (others => '0');
 
  ale_d <= '0';
  ale_2d <= '0';
  ale_3d <= '0';
 
elsif(rising_edge(clk)) then
 
  addr_in_d <= cpu_addr;
  addr_in_2d <= addr_in_d;
 
  ale_d <= ale;
  ale_2d <= ale_d;
  ale_3d <= ale_2d;
 
  if(ale_2d = '1' and ale_3d = '0') then  -- Detect the rising edge of Ale and..
    address <= addr_in_2d;                -- ..register in the address..
  elsif(inc_address = '1') then            -- ..or if inc address is active
    address <= address + 1;               -- increment it.
  end if;
 
end if;
end process;

It's good practice to register asynchronous signals in twice to guard against metastability. I then register ale in again to compare it with the first 'stable' version.

If the address is stable long before Ale goes active you probably don't have to register it in but it's a habit. In other applications you could adjust the number of times it's sampled depending on set up and hold times wrt Ale.

If your design is done correctly you should have exactly the same hardware behaviour from each re-build. Differing behaviour means the design is incorrect or something isn't constrained properly.

Again I hope this helps.

Nial.