Different results on hardware compared to simulator

The implementation for your design depends on the timing relationship between signals.

Even though ALE is called "Address Latch Enable", it does not have to be used as a latch enable, rather it can be used as a register enable.

The same goes for the read and write signals, if they are synchronous to the clock signal, you can use them combinatorially to create the address increment signal.

If the external bus is completely asynchronous to any clock you have access to, then the logic becomes quite different.

If you are using an FPGA that contains a PLL, then you can generally create an internal clock that can be used to oversample and synchronize external signals. If the processor interface has a wait-state control, then you can extend bus read/write cycles to meet timing.

So what bus are you trying to interface to?

Cheers,

Dave