Different results on hardware compared to simulator

I understand that any signal used as the edge to clock a register is considered a clock. I am getting warnings that the launch and latch times between source clock: ale and destination clock: clk are outside legal time range. Ale is basically asynchronous with the main clk. How can I tell it that? I used create_clock not create_generated_clock since ale has nothing to do with the main clk. I guess that is considered another clock domain.

Bidirectional Busses: OK, Got it. Don't use bidirectional busses inside the FPGA to communicate between modules. Just use a data_in and a data_out bus.

I will rewrite my code to do this.

I am beginning to see improvement with even partial timing constraints set. So far the hardware is working correctly. I will see if it behaves properly as more design changes are made.