Honored Contributor
Honored ContributorI have gone through the TimeQuest online course and I understand the basics. I am working through the main Quartus Interactive Tutorial on timing. But still have some puzzles.
My design uses a multiplexed address/data bus (data_io) with an address latch enable (ale), wr and rd signals. There is also a 14.7456 MHz clock coming into the FPGA which I use to run the internal processes. A cycle of writing to the FPGA would start with placing an address on the data_io, then set the ale high, then low again. The high time is about 1us so its much slower than the clock. The data_io is valid about 1us before the rising edge of the ale. A write cycle is virtually the same but uses the wr signal going high for 1 us. In TimeQuest I created the 14 MHz clock just fine. Now it thinks that ale and wr and rd are also clocks and I need to constrain them. Of course, they do not have a regular repeating cycle. There is only those 1us pulses occuring when we want to communicate with the FPGA. So how does one define that in terms of a clock? Also, I cannot control the relationship of the fast clock signal to the ale, wr, or rd signals. I created a "clock" that is the ale input port with a period of 2000ns (1us high time). So my clocks look like this: create_clock -name {clk_14Mhz} -period 67.817 -waveform { 0.000 33.908 } [get_ports {clk}] create_clock -name {ale} -period 2000.000 -waveform { 0.000 1000.000 } [get_ports {ale}] Should I just lengthen the period of the ale and set the fall time to 1000 to simulate closer to what the ale would be doing?
