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Altera_Forum
Honored Contributor
Honored ContributorDifferent results on hardware compared to simulator
I'm having trouble when I run my code on the actual Cyclone III FPGA. In the simulator it works fine. I have set up state machines to make sure that clock signals to registers are occurring after ple...
Altera_ForumHonored Contributor
Honored ContributorThis will be because the registers in the cyclone III have no asynchronous set and preset inputs, unlike earlier chips. So this behavious has to be emulated.
I suspect the problem is nothing to do with timing exactly, but poor design practice in the source code. If latches are being created then the problem will be timing issues that occur with such designs that cannot be looked at with time quest. Latches and asynchronous logic will also make the design unreliable and suseptable to temperature variations.
