Different results on hardware compared to simulator

I was able to eliminate the latch warnings. Code running on the hardware is still working illogically (or rather not working).

Is this warning a real concern:

Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

I eliminated this warning on a couple of registers at a lower level. Should I pursue this more?

I also get a bunch of warnings in the timing analysis of this type:

Warning (332060): Node: uart:rs485_port|baud_clk[0] was determined to be a clock but was found without an associated clock assignment.

It seems to occur for every signal that is used as an edge trigger to a always_ff block, like this:

always_ff @ (posedge reset_n, posedge baud_clk[0])

begin

blah,....

end

In that particular example the baud_clk is a 4 bit counter that is just being clocked by the main system clock (after it goes through another counter I use for deriving the desired baud rate * 16).

Is there a quick and easy way to set up the timing analysis so that it checks things properly?