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I have not done timing. Since the chip is running at such a slow clock rate (14 MHz, about 70 ns period)
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Try including a minimal .sdc file, eg., here's one I've copied and then edited to reflect your clock, edit the port name for the clock, and then edit the names of the reset and outputs that you do not care about (with regards to meeting clock-to-output delays):
# -----------------------------------------------------------------# Clock# -----------------------------------------------------------------# # 14MHz clock (70ns period)
set clk_period 70
# External clock (internal logic clock)
set clk clkin_14MHz
create_clock -period $clk_period -name $clk
# -----------------------------------------------------------------# Cut timing paths# -----------------------------------------------------------------# # The timing for the I/Os in this design is arbitrary, so cut all# paths to the I/Os, even the ones that are used in the design,# i.e., reset and the LEDs.#
# External asynchronous reset
set_false_path -from -to *
# LED output path
set_false_path -from * -to
The latch warning is also a worry. Fix your logic so that registers are used, not latches.
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At this point SignalTap would be difficult because I don't have access to the JTAG port without hacking the board (a flaw which I will correct on the board in the future).
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Lesson learned then, eh :)
Cheers,
Dave
Honored Contributor
