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Altera_Forum
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13 years ago

Different results on hardware compared to simulator

I'm having trouble when I run my code on the actual Cyclone III FPGA. In the simulator it works fine. I have set up state machines to make sure that clock signals to registers are occurring after ple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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What am I missing here that makes the code work incorrectly on the actual hardware?

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Missing synchronization logic between clock domains? Missing reset synchronizer logic. Timing constraints?

Does Quartus warn you about anything? Make sure all synthesis warning messages are resolved.

Does TimeQuest indicate all timing is met?

Rather than using LEDs to probe your design, use SignalTap II - this logic analyzer allows you to see much more of the internals of the design.

Cheers,

Dave