Difference between dedicated clock output pins & regular I/O?

There is a very fast connection from the PLL output to the dedicated clock outputs. It is fast and has very low jitter. Otherwise you will take the normal path of getting onto the global clock tree, getting off at the I/O and driving out. It's not so much skew that would degrade(since skew is in relation to something else), but jitter. The global clock tree and all it goes through will see more switching around it, more rise/fall variaion, etc. and will have more jitter.

That being said, I don't think it will be that bad. I see people using regular I/O as clock outputs all the time, and never heard of a problem. If you're doing a source synchronous output where the clock and data go together, you absolutely want to use a regular output so that your clock and data paths mimic each other. And these interfaces run at 300MHz, double-data rate. If you're driving something extremely susceptible to jitter, say an analog component, then you would probably favor the dedicated output. If you're doing source-synchronous, you want a regular I/O that's near the data. Everything else is probably a don't care.

Hi Rysc,

Thanks for your help in clarifying the difference. Appreciate it!

Gonna do some simple tests on the PLL output and increasing the frequency.

Thanks again.

@ Rysc

what about clock output like for an sdram chip clock input pin where you need to set the pll to a phase shift between the sdram clock and all the other sdram signals ? we had a design that failed due to not using a dedicated clock output pin for the sdram clock and after soldering two wires to swap signals that board run as intended.