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Your question is a little difficult to answer without knowing what sort of components you have added to your Qsys system.
Click on each of the options and look at the code generated.
Typically I just generate a simulation model (in VHDL or Verilog depending on what I am doing).
I then explicitly add BFMs or device models for testing.
For example, when testing Avalon-MM slave components, I explicitly add an Avalon-MM master BFM to the design, eg., take a look at this tutorial;
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Thanks Dave,
So basically if I chose to generate test-bench qsys system and test-bench simulation model, the tool would generate a wrapper system containing an instance of DUT and another instance of BFMs, however if I did your way, DUT and BFMs would be within a single instance (BFMs are now virtually a part of DUT), a simulation model of such a single instance is equivalent to the simulation model of the wrapper system right?
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