Devide in VHLD

Dear Tricky and Daixiwen

Could you check this code for me?

When I simulate by waveforms vector of Quartus, at Result_out, the final result is true but I have a lot of result

Ex: (-30)x(-6) = 180 but I saw, they have 16, 148, 180. (I attached this waveforms in this message)

I don't know this value.

Thanks before.

library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity Multvhdl is
Port (
     A,B      : In Signed(15 downto 0); --A*B
     Result_out   : Out Signed(31 downto 0);
     CLK     : In std_logic);
end Multvhdl;
Architecture structural of Multvhdl is
Signal Multiplicant,Multiplier  : Signed(15 downto 0);
Signal Result      : Signed(31 downto 0);
Signal CNT      : unSigned(3 downto 0);
Signal Sign      : unSigned(1 downto 0);
Begin
Process(clk)
Begin
if clk='1' and clk'event then 
    cnt<=cnt+"1";
    sign<="0" & (A(15)xor B(15)); --Check sign of A and B 
    if cnt="0000" then    
        Multiplicant<= ABS (A); 
        Multiplier<= ABS (B); 
    elsif cnt="0001" then  
        Result<=Multiplicant*Multiplier;
    elsif cnt="0010" then
        if sign = "00" then
           Result_out<=result;
        elsif sign = "01" then
           Result_out<= -result;
        end if;   
        cnt<="0000";
 end if;  
end if;
end process;
end structural;