Devide in VHLD

The loop is infinite if 'Devider' is 0. No synthesizer will be able to synthesize this. It will also probably give strange results with a negative divider.

While you are at it, you should use ieee.numeric_std and the signed and unsigned types rather than ieee.std_logic_signed. numeric_std is standard, makes it easier to mix signed and unsigned arithmetic, and makes the code more readable and maintainable.

As tricky said even if you fixed this, it will result in massive parallel hardware, which probably isn't what you want. If you don't need the result in a single clock cycle, you should consider unrolling the operation over several cycles to get a much smaller hardware footprint.