Devide in VHLD

Dear my friend

I use While loop to implement divide algorithm in VHDL. But I met an error. Could you help me to solve this problem.

Thank you very much.

This is my code:

library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
Entity Devide_Modelsim is
Port (
	Devidend,Devider 	: In std_logic_vector(7 downto 0);
	Quotients			: Out std_logic_vector(7 downto 0));
end Devide_Modelsim;
Architecture structural of Devide_Modelsim is
Signal Remainder 	: std_logic_vector(7 downto 0):=devidend;
Signal Result 		: std_logic_vector(7 downto 0);
Begin
Process(Remainder,Devider,result)
Begin
While (Remainder > Devider) loop 
	Result<=Result+"1";
	Remainder<=Remainder-Devider;
End loop;
	Quotients<=result;
end process;
end structural;

and this is error:

--- Quote Start ---

Error (10536): VHDL Loop Statement error at Divide.vhd(17): loop must terminate within 10,000 iterations

Error: Can't elaborate top-level user hierarchy

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings

Info: Allocated 324 megabytes of memory during processing

Error: Processing ended: Fri Dec 10 18:47:32 2010

Error: Elapsed time: 00:00:09

Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings

--- Quote End ---

In my opinion, this loop did not pass over 10.000 but it still error.