Hello, I am looking for a simple glue logic solution that has about 4k D-flip flops. The glue logic just involve simple counters, shift registers, and combination logic. But I need very tight timing data for the logic such as setup time, hold time, etc. I found that the MAXII datasheet has very detail timing data, but the Cyclone FPGA datasheet does not show any detail. All I can see from its handbook is that it can go up to a few hundred MHZ. But the MAXII might not have enough gates for my purpose. I do not want to install any software on my PC until I am sure I want to go for a particular device. I look at other competitors web site and similar things happen. Most CPLD datasheet provides detail timing, but most FPGA datasheet is very vague on timing information. BR - Henry

--- Quote Start --- Hello, I am looking for a simple glue logic solution that has about 4k D-flip flops. The glue logic just involve simple counters, shift registers, and combination logic. But I need very tight timing data for the logic such as setup time, hold time, etc. I found that the MAXII datasheet has very detail timing data, but the Cyclone FPGA datasheet does not show any detail. All I can see from its handbook is that it can go up to a few hundred MHZ. But the MAXII might not have enough gates for my purpose. I do not want to install any software on my PC until I am sure I want to go for a particular device. I look at other competitors web site and similar things happen. Most CPLD datasheet provides detail timing, but most FPGA datasheet is very vague on timing information. BR - Henry --- Quote End --- Hi Henry, the internal timings will not give you the answer your are looking for. The internal timings describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA. Have a look to : http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf In this document you will find at least some timings for the internal clock trees and a few other things. Kind regards GPK

Hi GPK, Thanks for your reply. So it goes back to the situation between choosing FPGA or CPLD. Does it mean that if I choose a high gate count FPGA and keep its utilization to be small enough, then I might be able to meet the timing requirement? If so, is there a typical plot of utilization versus usable clock rate? Or, the only way to find this out is to install the software, design the schematic, and run the simulation, and finally find that the device cannot meet my requirement? My circuit is actually very simple. It uses one single clock synchronize logic design, so what I need to know is the maximum achievable clock rate for the combinational logic plus the D flip flop delay (such as a synchronize 8-bit binary counter design), and it can be easily found out from most CPLD datasheet, but not for FPGA datasheet. The MAXII could fit my needs, but unfortunately, its logic units cannot be converted into RAM bits to realize small FIFO or dual-port RAM. I could use D flip flops as RAM, but the MAXII does not have such large device to choose from. Other's CPLD such as those from Lattice or Actel have configurable RAM bits. BR - Henry

--- Quote Start --- Hi GPK, Thanks for your reply. So it goes back to the situation between choosing FPGA or CPLD. Does it mean that if I choose a high gate count FPGA and keep its utilization to be small enough, then I might be able to meet the timing requirement? If so, is there a typical plot of utilization versus usable clock rate? Or, the only way to find this out is to install the software, design the schematic, and run the simulation, and finally find that the device cannot meet my requirement? My circuit is actually very simple. It uses one single clock synchronize logic design, so what I need to know is the maximum achievable clock rate for the combinational logic plus the D flip flop delay (such as a synchronize 8-bit binary counter design), and it can be easily found out from most CPLD datasheet, but not for FPGA datasheet. The MAXII could fit my needs, but unfortunately, its logic units cannot be converted into RAM bits to realize small FIFO or dual-port RAM. I could use D flip flops as RAM, but the MAXII does not have such large device to choose from. Other's CPLD such as those from Lattice or Actel have configurable RAM bits. BR - Henry --- Quote End --- Hi Henry, in case your design is ready I would run a P&R run with Quartus. It will give you all numbers you need. Kind regards GPK

Hi GPK, I only have the block diagram drawn up in PPT. Is it okay to run a simulation? Basically it is very simple, it has a 48 x 32 D-type flip flops, there are 48 data lines going into the flip flops inputs, and the flip flops are clocked serially to form a buffer that is 32 deep by 48 width. Once I receive a logic signal, it disable data loading and freeze the data inside these flip flops. Then the logic should load the D flip flops in each line into a shift register, so there should be 32 shift registers with a length of 48. Then I can slowly shift the data out from the shift registers to other IO pins. So this is the most critical part which require as high a speed as possible. The target clock speed for this block is 100MHz. I am hoping the EP4CE6 can do the job. Thanks! BR - Henry

--- Quote Start --- Hi GPK, I only have the block diagram drawn up in PPT. Is it okay to run a simulation? Basically it is very simple, it has a 48 x 32 D-type flip flops, there are 48 data lines going into the flip flops inputs, and the flip flops are clocked serially to form a buffer that is 32 deep by 48 width. Once I receive a logic signal, it disable data loading and freeze the data inside these flip flops. Then the logic should load the D flip flops in each line into a shift register, so there should be 32 shift registers with a length of 48. Then I can slowly shift the data out from the shift registers to other IO pins. So this is the most critical part which require as high a speed as possible. The target clock speed for this block is 100MHz. I am hoping the EP4CE6 can do the job. Thanks! BR - Henry --- Quote End --- Hi Henry, in Quartus you have a megawizard which offers some Ip blocks. Have a look to http://www.altera.com/literature/ug/ug_shift_register_ram_based.pdf Kind regards GPK

Device selection | Altera Community

12 Replies

Altera_Forum
Honored Contributor
16 years ago
Hi GPK,

Thanks for your reply. So it goes back to the situation between choosing FPGA or CPLD. Does it mean that if I choose a high gate count FPGA and keep its utilization to be small enough, then I might be able to meet the timing requirement? If so, is there a typical plot of utilization versus usable clock rate? Or, the only way to find this out is to install the software, design the schematic, and run the simulation, and finally find that the device cannot meet my requirement?

My circuit is actually very simple. It uses one single clock synchronize logic design, so what I need to know is the maximum achievable clock rate for the combinational logic plus the D flip flop delay (such as a synchronize 8-bit binary counter design), and it can be easily found out from most CPLD datasheet, but not for FPGA datasheet.

The MAXII could fit my needs, but unfortunately, its logic units cannot be converted into RAM bits to realize small FIFO or dual-port RAM. I could use D flip flops as RAM, but the MAXII does not have such large device to choose from. Other's CPLD such as those from Lattice or Actel have configurable RAM bits.

BR - Henry
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hello,

I am looking for a simple glue logic solution that has about 4k D-flip flops. The glue logic just involve simple counters, shift registers, and combination logic. But I need very tight timing data for the logic such as setup time, hold time, etc. I found that the MAXII datasheet has very detail timing data, but the Cyclone FPGA datasheet does not show any detail. All I can see from its handbook is that it can go up to a few hundred MHZ. But the MAXII might not have enough gates for my purpose. I do not want to install any software on my PC until I am sure I want to go for a particular device.

I look at other competitors web site and similar things happen. Most CPLD datasheet provides detail timing, but most FPGA datasheet is very vague on timing information.

BR - Henry

--- Quote End ---

Hi Henry,

the internal timings will not give you the answer your are looking for. The internal timings
describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA.

Have a look to : http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf

In this document you will find at least some timings for the internal clock trees and a few other things.

Kind regards

GPK

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Device selection

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