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Altera_Forum's avatar
Altera_Forum
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18 years ago

Device resource usage

Hi folks,

First time for me here, so let's introduce myself - my name is Michael and I work as an assistant at Technical University of Varna - Bulgaria.

Right now I am trying to implement a control logic in an 7000S device using a graphical editor and MAX II +PLUS development software. I am amazed though how fast the resource of the device is taken away. For example an 8 bit shift register plus two 8-bit latches and an 3 bit counter require 64 macrocells. Is that normal? What if I need a wider shifter, e.g. 16 or 32 bit wide? And I did not even start with my design - there is a plenty of functions I would like to add. Is there a way to minimize the resource cost and fit into a smaller (up to 64 macrocells) device? Thank you in advance for your answers!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hard to say without your code.

    What you describe looks like it should take only 8 + 16 +3 (27) macrocells & a few more as overhead to interconnect them. Depending on how they are interconnected, it might take twice that if the relationships are complex boolean functions.

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  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thank You very much for Your answer, Avatar!!!

    Lets summarize:

    Does that mean, that if I have to implement a 32 bit shift register, it will consume all the resuorces of my 7032, leaving no free macrocells to implement a 4 bit counter for example?

    Is there a way to have them both in my design and still fit into 32-macrocells device, e.g. some design (or pin assignment) settings or a special way of implementation (for example to use nands instead of flip-flops)?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Correct.

    32 F/F will take 32 Macrocells.

    You need to look at the structure of how a traditional CPLD is constructed.

    You have inputs.

    They feeed into a certain number of grouped macrocells.

    The macrocell is made up of a variable AND array which feeds a fixed OR function.

    (These care min-terms if you are doing classic truth table coverage)

    The result of the OR will feed [optionally] a F/F input.

    That output (either the OR or the FF) may beable to exit the CPLD on an output pin.

    It will also be able to loop around to feed the front end (like the input pins).

    Everyones CPLD is basically the same, some just offer various 'special paths' to allow for interesting 'detours' which can enhance their offering in some way.

    To answer your second question - No.

    (If you use the NANDS, then you will still 'burn' a Macrocell).

    I hope this helps you.

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    (if this is of value to you, can you figureout how to go and give me some reputation points?)
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Yep. It really clarifies that subject. Thanks again!

    --- Quote Start ---

    (if this is of value to you, can you figureout how to go and give me some reputation points?)

    --- Quote End ---

    I didn't get that one. :(
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    You should see a link labeled "Add to Avatar's Reputation" right above each of Avatar's posts. Click the link for the particular post that was helpful.