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Altera_Forum
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16 years ago

Design portability on a cyclone

Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Neither do I. Megafunction inference is sometimes mysterious... In this case, the constant type seems to be the problem. It's a kind of Quartus design compiler bug in my opinion.

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Hi FvM,

I agree with you, because for other device families it seems to work fine.

Kind regards

GPK