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Honored Contributor
Honored ContributorDesign portability on a cyclone
Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_ForumHonored Contributor
Honored ContributorOK !
It works properly you was right. I have made a mistake on how to modifie a file wich is include in a SOPC. Thank you VERY VERY much
