Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDesign portability on a cyclone
Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_ForumHonored Contributor
Honored ContributorI tried. Thank you. However I don't understand why it work.
Now I manage to make the gate level simulation with propagation time but : it doesn't work on hardware? I never saw that ... What can I do ?
