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Altera_Forum's avatar
Altera_Forum
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16 years ago

Design portability on a cyclone

Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I found, that there's exactly one dangerous warning in the Cyclone III report:

--- Quote Start ---

Warning: Synthesized away the following node(s):

Warning: Synthesized away the following RAM node(s):

Warning (14320): Synthesized away node "FDCT:U_FDCT|MDCT:U_MDCT|ROME:\G_ROM_ST1:0:U1_ROME|altsyncram:Mux11_rtl_15|altsyncram_0hv:auto_generated|ram_block1a0"

--- Quote End ---

It's originated from an instance of rome.vhd.

By changing the table definion in rome.vhd from 

  constant rom : ROM_TYPE :=
to 

  signal rom : ROM_TYPE :=

the above warning vanished and the ROM implementation was changed from Mux11_rtl_15 to rom_rtl_15. I didn't set up the ModelSim simulation, but I hope, the problem can be solved this way.