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Honored Contributor
Honored ContributorDesign portability on a cyclone
Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- But I can't evaluate where the problem come from because I am in gate level simulation. --- Quote End --- You should be still able to assign the nets to original design entities and try to determine what's the 'X' source in your design.
