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Altera_Forum
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16 years ago

Design portability on a cyclone

Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Yes

data_out ='X'

But I can't evaluate where the problem come from because I am in gate level simulation. What can I do ?

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Hi,

it looks for me as an synthesis issue, because the synthesis engine are different for the FPGA families. Can you try an older or newer Quartus version ?

Kind regards

GPK