Honored Contributor
Honored ContributorI don't know much about the partitioning stuff but my first step would be to feed your RTL through component editor so that it shows up as a Qsys component (Altera name for packaged up IP). It will then show up as a component on the left side of the screen like the rest of the IP and then you integrate it by connecting the H2F master to the slave port of your IP core. Qsys will generate any necessary logic to adapt your IP to the HPS master interface and you don't have to worry about it yourself by trying to manually integrate it.
Assuming your IP core has a clock, reset, AXI slave, and some signals that you want to connect to outside of the Qsys system you would create a Qsys component using a tool called "Component Editor" in Qsys. You would create a clock input, reset input, AXI slave, and conduit set of interfaces and then map the appropriate ports of your RTL to one of those four interfaces. You associate the clock and reset to the AXI interface which lets the tools know what clock/reset domain your AXI slave operates on. If your RTL has parameters... or whatever they are called in VHDL then those will get bundled up into the component description (.tcl file) and become GUI options when you instantiate the component in your system. This will become much more clear if you go through chapter 6 of this document: http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf This would probably be worth taking a look at too even though it's only Avalon based: http://www.altera.com/education/training/courses/oqsys3000
