design partition export/import

I don't know much about the partitioning stuff but my first step would be to feed your RTL through component editor so that it shows up as a Qsys component (Altera name for packaged up IP). It will then show up as a component on the left side of the screen like the rest of the IP and then you integrate it by connecting the H2F master to the slave port of your IP core. Qsys will generate any necessary logic to adapt your IP to the HPS master interface and you don't have to worry about it yourself by trying to manually integrate it.

Assuming your IP core has a clock, reset, AXI slave, and some signals that you want to connect to outside of the Qsys system you would create a Qsys component using a tool called "Component Editor" in Qsys. You would create a clock input, reset input, AXI slave, and conduit set of interfaces and then map the appropriate ports of your RTL to one of those four interfaces. You associate the clock and reset to the AXI interface which lets the tools know what clock/reset domain your AXI slave operates on. If your RTL has parameters... or whatever they are called in VHDL then those will get bundled up into the component description (.tcl file) and become GUI options when you instantiate the component in your system.

This will become much more clear if you go through chapter 6 of this document: http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf This would probably be worth taking a look at too even though it's only Avalon based: http://www.altera.com/education/training/courses/oqsys3000

Hi,

Thank you very much for your reply. The solution worked.

I was able to create my IP core through the new component tool of the qsys. My IP had both AXI master and slave in the same interface. I added multiple clocks of same clock domain to manage the clocks for both AXIs'.

Although after adding IP in my qsys system, I'm unable to set the address map for the H2F master bus. By default, it takes 0x0000_0000 - 0xffff_ffff even if I enter different values.

Could you please direct me to where I can find the addressing mapping of the h2f port? I can add this address into the generated source files from qsys to resolve the address map problem. Thanks.

Best Regards,

Nitin.

From the HPS side the H2F bridge lives at address 0xC000_0000 so the stuff you connect to it would be offset by that amount when you go to access it from the HPS.

By the sounds of it the address width of your component is 32-bit and that's why it is taking up such a large range. The H2F bridge can only access a total span of around 1GB so you'll need to make the address width of your custom component less than 30-bit. Most peripherals have a handful of registers so they don't typically require a large address span.

Hi,

Thanks again. The error was due to the address space of the custom peripheral. The problem was solved once the range was reduced. ^_^

Thanks,

Nitin.