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Altera_Forum's avatar
Altera_Forum
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11 years ago

design partition export/import

Hi, I'm trying to add a custom logic in a qsys generated system. I synthesized my design files and exported it as a design partition to create the (.qxp file). I created a qsys system co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

Thank you very much for your reply. The solution worked.

I was able to create my IP core through the new component tool of the qsys. My IP had both AXI master and slave in the same interface. I added multiple clocks of same clock domain to manage the clocks for both AXIs'.

Although after adding IP in my qsys system, I'm unable to set the address map for the H2F master bus. By default, it takes 0x0000_0000 - 0xffff_ffff even if I enter different values.

Could you please direct me to where I can find the addressing mapping of the h2f port? I can add this address into the generated source files from qsys to resolve the address map problem. Thanks.

Best Regards,

Nitin.