delay

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hello,

i have a little question for you, guys....how can i put a delay between two if instructions (the second if to be executed after a few seconds)..........the code is in verilog.

thx, tastax

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Use counter.

// very simpy without reset.

reg [7:0] cnt;

always @ (posedge clk) begin

cnt <= cnt + 1'b1;

if(condition1 && (cnt == 7'h0))begin ..... end

if(condition2 && (cnt == 7'h3))begin ..... end

if(condition3 && (cnt == 7'h13))begin ..... end

end